In recent years, DRAM (dynamic random access memory) technology has progressed dramatically. Device storage capacities have increased from 1 Kbits per chip to 64 Mbits per chip, a factor of 64,000. However, DRAM performance has not maintained pace with these density changes, since access times have decreased by a factor of approximately five. During this same time period, microprocessor performance has increased by several orders of magnitude. This disparity between the speed of the microprocessors and the access time associated with DRAMs has forced system designers to create a variety of expensive and often complicated hierarchical memory techniques, such as SRAM (static random access memory) caches and parallel arrays of DRAMs. Some high performance graphics systems rely on expensive frame buffers to provide the necessary bandwidth for communicating with the memory devices.
Rambus Inc. has developed a new chip-to-chip bus, referred to as the “Direct Rambus Channel”, that operates up to ten times faster than conventional DRAMs. The Direct Rambus Channel (the channel) connects memory devices to other devices such as microprocessors, digital signal processors, graphics processors and ASICs (application-specific integrated circuits). The channel uses a small number of very high speed signals to carry all address, data, and control information.
FIG. 1 illustrates a known memory module 100 containing multiple memory devices and a single channel coupling the memory devices to one another. Memory module 100 typically includes a substrate 102, such as a multi-layered printed circuit board (PCB) that supports multiple memory devices 104 mounted to the substrate. In this example, each memory device 104 is a Rambus DRAM (or “RDRAM®”), developed by Rambus Inc. of Mountain View, Calif. The memory devices are coupled to one another by a Direct Rambus Channel 106. Data flows into channel 106 on the left side of module 100, as oriented in FIG. 1. Data flows along channel 106, past the four RDRAMs 104, and out the right side of module 100. In a typical configuration, one or more modules 100 are supported by a motherboard (not shown), which includes a memory controller. Each of the four RDRAMs 104 can retrieve data from channel 106 and transmit data to other devices using channel 106.
Channel 106 shown in FIG. 1 provides a high bandwidth communication path for address, data, and control information associated with one or more of the four RDRAMs 104. Channel 106 includes multiple conductors, two of which are identified by the reference numbers 106A and 106B. As shown in FIG. 1, the channel conductors follow a ninety degree bend at each end of the substrate 102. Thus, the lengths of the various conductors in channel 106 are not equal. For example, the length of conductor 106A is greater than the length of conductor 106B in the same channel. This unequal routing of conductors in channel 106 causes problems with the timing of signals propagating on the channel because different signals arrive at memory device 104(1) at different times due to the unequal conductor lengths. Similarly, the conductors between memory device 104(4) and the channel output are unequal in length, leading to timing problems with signals on the channel output. To compensate for the unequal channel conductor lengths, the conductors may be routed on substrate 102 in such, a manner that each conductor is approximately the same length. Attempting to route conductors such that each conductor is approximately the same length is tedious and time-consuming. Additionally, such routing of conductors increases the cost and complexity of the substrate 102 (e.g., by requiring additional layers of conductors and additional vias between layers).
Alternatively, if the channel conductors are maintained at unequal lengths, then the processing of signals from the channel must be delayed for a period of time that allows the signal on the longest conductor to reach the appropriate device (e.g., memory device). This alternative slows the operation of the overall memory system by causing an added delay to compensate for the worst case delay on the channel.
The memory module 100 shown in FIG. 1 is also limited to a single channel 106 on each side of the substrate 102 (i.e., a maximum of two channels per memory module). Thus, all memory devices on one side of the substrate 102 share a common channel, which is limited to a particular bandwidth. The speed at which data can be stored to or retrieved from the memory devices 104 is limited by the bandwidth of the single channel.
The memory architecture described herein addresses these and other problems by providing an architecture in which all channel conductors are substantially the same length. Further, the memory architecture described herein supports the use of multiple channels on each side of a substrate, thereby increasing the overall bandwidth.